1. Field of Invention
The invention relates to static random access memory (SRAM) and, more particularly, to a compact and low-power SRAM with improved read static noise margin (SNM).
2. Description of Related Art
Decreasing the supply voltage can effectively reduce the power consumption of conventional static random access memory (SRAM). However, it is unfortunate that the decrease in supply voltage can also result in degraded read stability and, hence, can lead to increased fail-bit rate. As shown in FIG. 8, the butterfly curve showing the skewed read SNM of the conventional SRAM for different combinations of the process corner and temperature indicates the cause of the problem in the fail-bit rate. Motivated by this, there have been numerous SRAM architectures currently demonstrated in the literature which focus on making better tradeoff between the power dissipation and supply voltage, and it has been proved that they were able to improve the read SNM.
However, despite their effectiveness, these conventional SRAM architectures also come with the penalty of increased implementation area and design complexity. For example, one of the conventional SRAM architectures, termed dual-boosted cell based SRAM, was designed to improve read SNM at low supply voltage. However, the techniques of the architecture are very likely to cause transistor breakdown. Moreover, owing to the needs of multiple supply voltages and accurate control, such a design in the prior art is with increased circuit complexity as compared to the conventional SRAM structure, leading to increase in implementation area.
Furthermore, FIG. 8 is a conventional schematic diagram illustrating different process corners and temperatures for read SNM according to the conventional SRAM architecture. In summary, the conventional SRAM architectures have many problems such as low read stability, high power, low speed and large area. Especially, in modem manufacturing processes, the supply voltage descends by a wide margin. Despite that, the decrease in the supply voltage can facilitate the decrease in the dynamic power consumption of the SRAM. When the SRAM perform a read operation at high speed, stability is a key factor about performance of the SRAM. Thus, the need for improvement still exists.